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CDMA Cellular Phone Power Management IC
POWER MANAGEMENT Description
The SC905A is a power management integrated circuit (PMIC) designed for the latest CDMA chip sets. The device provides four general purpose low dropout regulators (LDOs), and five low noise LDOs designed for analog circuits. The VMOT LDO can be used as a general purpose regulator or as an adjustable motor drive output that can supply up to 150mA to drive a vibrator motor. Each LDO's enable and output voltage are controlled via the I2C bus. The VTCXO output has an external enable pin that can be used instead of the register bit when timing is critical for minimizing sleep current. The VMOT also has an external enable pin for additional flexibility. Initial power-on is achieved by activating either the ON button, the battery charger, or the HFPWR signal, and the PGOOD input is used by the microprocessor to latch power on or disable the device. The thermally-efficient MLPQ-32 package combined with miniature ceramic bypass capacitors minimize required PCB area, making the SC905A ideal for space-conscious portable applications.
SC905A
Features
9 LDO Linear Regulators CORE: 1.35V - 2.90V @ 300mA ANA: 2.55V - 2.90V @ 200mA PAD: 1.75V - 3.30V @ 300mA RX: 2.75V - 3.10V @ 150mA TX: 2.75V - 3.10V @ 150mA TCXO: 2.75V - 3.10V @ 80mA PLL: 2.75V - 3.10V @ 80mA Camera: 1.75V - 3.30V @ 100mA Motor Drive: 1.75V - 3.30V @ 150mA I2C Interface for Microprocessor Control Less than 1A Quiescent Current in Shutdown 65dB PSRR for Analog LDOs Over-Temperature Protection Power-On Control Small 5mm x 5mm 32-Pin MLPQ Package
Applications
CDMA Cellular Handsets PDAs/Smartphones Wireless VOIP Handsets
Typical Application Circuit
VBAT
Battery Charger Circuit Handsfree Option
ON/OFF
SC905A
VBAT IN 1 CHPWR IN 2 EN_TCXO IN 3 EN_MOT IN 4 IN 5 IN 6 ON DVIN HFPWR VCORE PGOOD VPAD SDA VANA SCL VTCXO PWRON VPLL RESB VTX VRX VMOT VCAM BP VPSEL VCSEL AGND DGND
10F B A TTE RY
1F
TCXO + Synthesiser PLL
1F
Transmitter Section
1F 1 F 1F
PA
Receiver Section Baseband Processor
LNA
0. 1F
MOTOR
1F
1 F
1F
Camera Module Audio Processing Keypad
Digital Interface
June 7, 2006
1
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SC905A
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Input Supply Voltage Digital Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Peak IR Reflow Temperature Storage Temperature Thermal Resistance Junction to Ambient ESD Protection Level(2)
(1)
Symbol VIN VDIG TA TJ TLEAD TSTG JA ESD
Maximum -0.3 to +7 -0.3 to VIN+0.3 -40 to +85 -40 to +125 260 -60 to +150 26 2
Units V V C C C C C/W kV
Notes: (1) Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Unless otherwise noted VIN = 3.7V, TA = -40 to +85C. Typical values are at TA = +25C.
Parameter General Supply Voltage Shutdown Current Quiescent Supply Current Supply Bypass Capacitor Start-Up Time Under-Voltage Lockout Over-Temperature Digital Inputs Digital Input Voltage(1) Digital Input Current Digital Outputs Digital Output Voltage(2) LDO Regulator (CORE) - 300mA Output Voltage Accuracy(3) Current Limit Default At Start-Up: ON
Symbol
Condition
Min
Typ
Max
Units
VIN ISD ISU ISTBY CVCC tSU UVLO OT
2
2.7 ON = 0V, HFPWR = 0V, CHPWR = 0V, PGOOD = 0V Default Start-Up Mode I C, VREF Active, All Outputs Disabled At Each Power Input Pin CBP = 0.1F Descending, Hysteresis = 50mV Hysteresis = 20C 300 30 1 25 2.5 160
5.5 1
V A A
60
A F ms V C
VIL VIH IDIG VOL VOH Logic Level High or Low 1.25 -0.2
0.4 0.2
V V A
ISINK = 1.2mA ISOURCE = 0.5mA, VPAD 1.8V 90
2 98
10
%VPAD %VPAD
VOUT ILIM VOUT-HI VOUT-LO
1.35V VOUT 2.90V, IOUT = 1mA, VOUT +0.35V VIN 5.5V VCORE = 0V VCSEL - High VCSEL - Low 2
-75 350 1.80 1.35
+75 900
mV mA V V
(c) 2006 Semtech Corp.
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SC905A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Symbol Condition Min Typ Max Units LDO Regulator (CORE) - 300mA (Cont.) Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio LDO Regulator (PAD) - 300mA Output Voltage Accuracy(3) Current Limit Default at Start-Up: ON Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio LDO Regulator (ANA) - 200mA Output Voltage Accuracy(4) Current Limit Default At Start-Up: ON Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (TCXO) - 80mA Output Voltage Accuracy(4) Current Limit Default At Start-Up: ON Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise (c) 2006 Semtech Corp. VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRTCXO en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 80mA VOUT = 3.10V, IOUT = 80mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1F, COUT = 1F 3 2.75V VOUT 3.10V, IOUT = 1mA, VOUT +0.35V VIN 5.5V VTCXO = 0V -75 250 3.05 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB VRMS www.semtech.com VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRANA en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 200mA VOUT = 2.90V, IOUT = 200mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA f = 10Hz to 100kHz, IOUT = 50mA, CBP = 0.1F, COUT = 1F 2.55V VOUT 2.90V, IOUT = 1mA, VOUT +0.35V VIN 5.5V VANA = 0V -75 250 2.60 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB VRMS VOUT ILIM VOUT-HI VOUT-LO REGLINE REGLOAD VDO PSRRPAD 1.75V VOUT 3.30V, IOUT =1mA, VOUT +0.35V VIN 5.5V VPAD = 0V VPSEL - High VPSEL - Low IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 300mA VOUT = 3.30V, IOUT = 300mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA -75 350 3.00 2.20 2.5 -3 300 50 12 -30 350 +75 900 mV mA V V mV mV mV dB REGLINE REGLOAD VDO PSRRCORE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 300mA VOUT = 2.90V, IOUT = 300mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA 2.5 -3 300 50 12 -30 350 mV mV mV dB
SC905A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter LDO Regulator (TX) - 150mA Output Voltage Accuracy(4) Current Limit Default At Start-Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (RX) - 150mA Output Voltage Accuracy(4) Current Limit Default At Start-Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (CAM) - 100mA Output Voltage Accuracy(3) Current Limit Default At Start-Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio LDO Regulator (PLL) - 80mA Output Voltage Accuracy(4) Current Limit (c) 2006 Semtech Corp. VOUT ILIM 2.75V VOUT 3.10V, IOUT = 1mA, VOUT +0.35V VIN 5.5V VPLL = 0V 4 -75 250 +75 650 mV mA VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRCAM IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 100mA VOUT = 3.30V, IOUT = 100mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA 1.75V VOUT 3.30V, IOUT = 1mA VOUT +0.35V VIN 5.5V VCAM = 0V -75 250 2.20 2.5 -3 200 50 12 -20 250 +75 650 mV mA V mV mV mV dB VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRRX en IOUT = 1mA, VOUT+0.35V < VIN < 5.5V 1mA < IOUT < 150mA VOUT = 3.10V, IOUT = 150mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA f = 10Hz - 100kHz, IOUT = 50mA, CBP= 0.1F, COUT = 1F 2.75V VOUT 3.10V, IOUT = 1mA, VOUT +0.35V VIN 5.5V VRX = 0V -75 250 3.05 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB VRMS VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRTX en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 150mA VOUT = 3.10V, IOUT = 150mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1F, COUT = 1F 2.75V VOUT 3.10V, IOUT = 1mA, VOUT +0.35V VIN 5.5V VTX = 0V -75 250 3.05 2.5 -3 200 65 45 12 -20 250 +75 650 mV mA V mV mV mV dB VRMS Symbol Condition Min Typ Max Units
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SC905A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Default At Start-Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (MOT) - 150mA Output Voltage Accuracy(3) Current Limit Default at Start-Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio VOUT ILIM VOUT REGLINE REGLOAD VDO PSRRMOT IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 150mA VOUT = 3.30V, IOUT = 150mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA 1.75V VOUT 3.30V, IOUT = 1mA, VOUT +0.35V VIN 5.5V VMOT = 0V -75 250 1.80 2.5 -3 200 50 12 -20 250 +75 650 mV mA V mV mV mV dB Symbol VOUT REGLINE REGLOAD VDO PSRRPLL en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 1mA < IOUT < 80mA VOUT = 3.10V, IOUT = 80mA f = 10Hz - 1kHz, COUT = 1F, IOUT = 50mA f = 10Hz - 100kHz, I OUT = 50mA, CBP= 0.1F, COUT = 1F Condition Min Typ 3.05 2.5 -3 200 65 45 12 -20 250 Max Units V mV mV mV dB VRMS
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SC905A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Symbol Condition Min Typ Max Units
I2C Interface(5) Interface complies with slave mode I2C interface as described by Philips I2C specification version 2.1 dated January, 2000. Digital Input Voltage SDA Output Low Level Digital Input Current Hysteresis of Schmitt Trigger Inputs Maximum Glitch Pulse Rejection I/O Pin Capacitance I2C Timing(5) Clock Frequency SCL Low Period SCL High Period Data Hold Time Data Setup Time Setup Time for Repeated START Condition Hold Time for Repeated START Condition Setup Time for STOP Condition Bus-Free Time Between STOP and START RESET Timeout Delay Power-up Delay Between PAD, ANA, TXCO Maximum Glitch Pulse Rejection Interface Start-up Time SCL tLOW tHIGH tHD_DAT tSU_DAT tSU_STA tHD_STA tSU_STO tBUF tRD tDELAY tSP tEN Bus Start-up Time After EN Pin is Pulled High Delay Between Each Output Activating 1.3 0.6 0 100 0.6 0.6 0.6 1.3 75 100 100 50 350 125 400 440 kHz s s s ns s s s s ms s ns s IDG VHYS tSP CIN VIL VIH IDIN (SDA) 3mA -0.2 0.1 50 10 1.25 0.4 0.2 0.4 V V V A V ns pF
Notes: (1) Applies to pin names, ON, HFPWR, CHPWR, PGOOD, VCSEL, VPSEL, EN_MOT, EN_TCXO. (2) Applies to pin names, PWRON, RESB. (3) For VOUT settings see Table A. (4) For VOUT settings see Table B. (5) Guaranteed by design. (c) 2006 Semtech Corp. 6 www.semtech.com
SC905A
POWER MANAGEMENT Pin Configuration Ordering information
DEVICE
VMOT VCAM VTCXO VANA VRX IN3 IN4 IN5
PACKAGE MLP 5x5 32L Evaluation Board
SC905AMLTRT(1)(2) SC905AEVB
24 23
VTX IN6 VPLL AGND VBAT BP PGOOD RESB
32
IN2 VCORE IN1 VPAD ON HFPWR SDA SCL
31
30 29
28
27
26
25
1 2 3 4 5 6 7 8 9
DGND
TOP VIEW
22 21 20
Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant.
T
19 18 17
10
DVIN
11
CHPWR
12
EN_TCXO
13
EN_MOT
14 15 16
PWRON VPSEL VCSEL
MLPQ32: 5X5 32 Lead
Marking Information Top Marking
905A yyww xxxxxx xxxxxx
yy = two digit year of manufacture ww = two digit week of manufacture xxxxxx = Semtech Lot Number
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SC905A
POWER MANAGEMENT Pin Descriptions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 T
Pin Name
IN2 VCORE IN1 VPAD ON HFPWR SDA SCL DGND DVIN CHPWR EN_TCXO EN_MOT VPSEL VCSEL PWRON RESB PGOOD BP VBAT AGND VPLL IN6 VTX VTCXO IN5 VRX VANA IN4 VCAM IN3 VMOT Thermal Pad
I/O
Input Output Input Output Input Input Input/Output Input Input Input Input Input Input Input Output Output Input Output Input Output Input Output Output Input Output Output Input Output Input Output -
Pin Function
Input voltage terminal to VCORE LDO. 300mA LDO output for MSM core processor supply. Input voltage terminal to VPAD LDO. 300mA LDO PAD output to MSM I/O circuits. Active high power on/off key. When the push button is closed it is shorted to battery. Power on input from accessory, active high. Bi-directional open drain digital I/O. I2C serial data. Digital input. I2C serial clock. Digital ground. Main digital input voltage terminal. Logic input. OR'd with ON and HFPWR. Logic input. External enable for VTCXO LDO. State is recorded in bit 0 of the status register. Logic input. External enable for VMOT LDO. State is recorded in bit 2 of the status register. Default control for VPAD LDO supply. Ground for 2.20V default, tie high for 3.00V. Default control for VCORE LDO supply. Ground for 1.35V default, tie high for 1.80V. Logic OR output of ON, HFPWR and PGOOD. Active high. Reset output. Active low. Logic input signal from MSM to indicate power is good, latches the SC905A on. Low disables the SC905A. LDO bypass output. Bypass with a 0.1F capacitor. Main battery supply input terminal. Analog ground pin. LDO output for PLL power. Input voltage terminal for VPLL & VTX LDOs. LDO output for transmitter power. LDO output for TCXO power. Input voltage terminal for VTCXO & VRX LDOs. LDO output for receiver power. LDO output for analog power. Input voltage terminal to VANA LDO. LDO output for camera power. Input voltage terminal to VCAM & VMOT LDOs. LDO output voltage for vibrator motor power. Can also be a general purpose output. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
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SC905A
POWER MANAGEMENT Block Diagram
19
BP
CHPWR ON HFPWR PGOOD
11
PWRON Logic
5 6
VREF OT
UVLO
18
VPAD
PWRON
16
VPAD
RESB
17
RESET
EN
3
PAD
EN
IN1 VPAD IN2 VCORE IN3 VCAM
4
1
CORE
EN REG EN CTRL EN
2
31 30
CAM
EN EN
7
I2C Registers & Control
SDA SCL VPSEL VCSEL
MOT
EN
8
I C Interface
32
VMOT IN4 VANA IN5 VTCXO
29
14
ANA
EN
15
2
28
26 25
TCXO
EN
EN_MOT EN_TCXO
13
RX
12
27
VRX IN6 VPLL
EN
23
VBAT DVIN DGND AGND
20
PLL
EN
22
10
9
TX
24
VTX
21
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SC905A
POWER MANAGEMENT Applications Information
General Description The SC905A includes nine low dropout (LDO) voltage regulators to provide complete power regulation capability for CDMA handsets or other portable electronic equipment. Five of the LDOs are designed to be used with analog circuitry such as audio, radio frequency, or oscillator circuits. These devices have very low noise levels and high power supply rejection. The output voltage range for four of these LDOs, VTCXO, VPLL, VTX and VRX, is 2.75V to 3.1V in 50mV steps, and for the fifth, VANA, the output voltage range is 2.55V to 2.9V in 50mV steps. The TCXO LDO has the additional feature of an external enable, EN_TCXO, which can be used when timing is critical. Two other LDOs are general purpose regulators designed to be used with digital circuits. The noise requirements for these LDOs are relaxed, but their voltage range is expanded to cover the wide range of voltages needed for different types of functions. The outputs for these LDOs are VCORE and VPAD. Two other LDOs are general purpose regulators that can be used with other peripheral circuits. The VMOT and VCAM outputs can be programmed to supply from 1.75V to 3.3V in 50mV steps. The VMOT output is specifically designed to drive a vibrator motor. This output can supply up to 150mA at any of the output voltage settings, allowing designers the flexibility to select the output voltage that provides maximum vibration. The VMOT output also has its own external enable, EN_MOT, to allow greater flexibility. When not used in conjunction with a vibrator, this output can be used as a general purpose digital regulator. The VCAM output is capable of supplying up to 100mA to drive a digital camera module or any other peripheral circuit found in a portable application. Power-On Control The SC905A is activated when the ON pin is pulled high, provided that the input voltage is within the specified operating range. The ON pin responds to logic-high edge triggering to power up the handset. The rising edge ON signal is latched when the CORE, PAD, ANA, and TCXO LDOs are turned on and PGOOD goes high. When the PAD LDO output voltage reaches 77% of its regulation point, the reset timer starts and the RESB signal transitions high after delay of typically 100ms. After a successful power up sequence, any subsequent condition that toggles RESB (e.g. VPAD short-circuit, over-temperature, under voltage lockout, I2C disable of VPAD) will see a delay in the RESB transition back to high of typically 250ms. The microprocessor then raises PGOOD high to keep the SC905A powered on. There is no time limit for the MSM to activate PGOOD. If the MSM fails to raise PGOOD before the ON switch is released, the SC905A will transition back into standby mode. Once the phone is powered on, the SC905A can only be directly powered off when the PGOOD signal goes low. Therefore, if the ON pin transitions high when the PGOOD signal is high, the LDOs and RESB signal will remain in their state until the microprocessor pulls the PGOOD signal low. Once the PGOOD signal is low, all the LDOs immediately power off and all the logic resets to the shutdown condition. The SC905A can be indirectly powered off by using the I2C command to turn off the core supply. This will result in a loss of power to the MSM causing PGOOD to go low, thus disabling the SC905A. The HFPWR and CHPWR pins operate identically to the ON pin. These pins provide alternative sources for activating power so that remote devices such as battery chargers or system connector pins can be used to enable the device. LDO Programmable Output Voltage The output voltage of each LDO regulator is programmable. Each LDO has a program voltage register that can be accessed through the I2C interface and the output voltage adjusted as necessary. (See the Tables on pages 14, 15 and 16 for more information.) ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by setting their respective on/off bits to 1 and disabled by setting the on/off bits to 0. This allows for on/off control with a single write command. The register data is maintained when an on/off bit is toggled, but all programmed information will be lost when the PGOOD input goes low. It should be noted that the enable signal control from the I2C for LDOs TCXO and MOT are OR'd with their respective external enable signals EN_TCXO and EN_MOT. This
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SC905A
POWER MANAGEMENT Applications Information (Cont.)
means that these LDOs are on when there is a `1' in their respective bit locations (register 6, bit 3 for VTCXO, register 2, bit 6 for VMOT), or if their external enable pins are pulled HIGH. To turn these LDOs off the I2C on/off control bit must be `0' and the external enable must be pulled LOW. The state of EN_TCXO and EN_MOT can be established by reading bits 0 and 2, respectively, in the Status Register. VCSEL & VPSEL Pin The VCSEL & VPSEL pins set the default voltage of CORE and PAD LDOs respectively. When the VCSEL pin is set to VIN the default voltage for the CORE LDO is 1.80V. When this pin is set to GND the default voltage for the CORE LDO is 1.35V. Likewise, when the VPSEL pin is set to VIN the default voltage for the PAD LDO is 3.00V. When this pin is set to GND, the default voltage for the PAD LDO is 2.20V. In both cases the VCSEL and VPSEL pins must be tied to GND or VIN prior to the device being powered on. This voltage cannot change on the fly by switching the pin voltage between VIN or GND once the device is on. The voltage can be changed from its default state after start-up by writing to the appropriate voltage code register. Active Shutdown The shutdown control bits determine how the on-chip active shutdown switches behave. Register 7 is the active shutdown control register and is used to control the shutdown behavior. Each LDO has a specific shutdown bit assigned to it. When the active shutdown bit is enabled (set to 1), the output capacitance on the LDO output is discharged by an on-chip FET when the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default state for each LDO active shutdown bit is on. Default Status Bit In many multi-threaded environments it is necessary to maintain synchronization between the host micro-controller and the target IC. The SC905A has a default status bit (DSB) that will facilitate this task. The DSB can be useful in keeping the MSM and the SC905A synchronized. However, this is only useful if the MSM is powered by an external switching regulator such as Semtech's SC190A switching regulator. The DSB is bit 7 of register 0, and shares this register space
(c) 2006 Semtech Corp. 11
with the PAD voltage control bits. The DSB is only set to 1 during power-up to indicate that the part is set to the default state. Moreover, the DSB cannot be written to a 1 through the I2C interface the way the other bits in this register can; it can only be cleared to 0 through the I2C interface. This feature prevents a software race condition by always writing to register 0 with bit 7 high when changing the PAD control voltage. To clear the bit simply write a 0 to bit 7. Applying the DSB Upon power-up, the SC905A LDOs and internal registers are set to their default state. The DSB is set to a 1 to indicate that the SC905A is in its default state. Upon reading this defaulted state condition, the MSM knows to perform whatever synchronization is needed to set the SC905A into a known user state. This user state is entered by a two-stage process. 1) The MSM writes a 0 to the DSB indicating its desire to modify the state of the SC905A. It then writes all of the correct register information to the SC905A to set it to the user state. 2) The MSM reads back all of the information to verify the data. Then it reads back the DSB again to ensure it is still set to 0. This verifies that no reset took place during the time that the multiple writes and read verifications happened. If the DSB has been reset to 1, this process needs to be repeated since the chip was reset sometime during the initialization. Once the MSM and the SC905A are synchronized, the DSB can be read back as a status check periodically, as needed. If it is ever set back to the default state, a new synchronization process is required. This handshake-style protocol makes sure that the MSM and SC905A are always synchronized. LDO Power-On Sequence When the SC905A first turns on, the four LDOs that default on are sequenced in the following fashion: 1) CORE, 2) PAD, 3) ANA, 4) TCXO. During the power-on sequence, there is a 200s delay between CORE and PAD to allow the output of CORE to reach 1.2V before PAD is turned on, a delay of 100s between PAD and ANA turning on, and a delay of 100s between ANA and TCXO turning on. This process eliminates large voltage spikes across the battery supply during power-up. (For further information on LDO power on sequencing, refer to the Timing Diagram on page 19.)
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SC905A
POWER MANAGEMENT Applications Information (Cont.)
Protection Circuitry The SC905A contains protection circuitry that prevents the device from operating in an unspecified state. These include Under-voltage Lockout Protection, Over-temperature Protection and Short-circuit Protection. Under-Voltage Lockout The SC905A provides an under-voltage lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. When the battery voltage drops below the UVLO threshold, as defined in the Electrical Characteristics section, the LDOs are disabled and RESB is held low. When the battery voltage is increased above the hysteresis level, the LDOs are re-enabled into their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905A will shut down. When powering-up with a battery voltage below the UVLO threshold, RESB will be held low. Over-Temperature Protection The SC905A provides an internal over-temperature (OT) protection circuit that monitors the internal junction temperature. When the temperature exceeds the OT threshold as defined in the Electrical Characteristics section, the OT protection disables all the LDO outputs, holds the RESB signal low and sets the OTF bit low in the status register. When the junction temperature drops below the hysteresis level, the OT protection resets the OTF bit high and re-enables all the LDOs in their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905A will shut down. This is only useful if the MSM is not powered by the SC905A, since during an OT fault the MSM will lose power. An external switching regulator such as Semtech's SC190A could power the MSM in the case where monitoring the OTF bit is desired. Short-Circuit Protection Each LDO output has short-circuit protection. If any output is short-circuited to ground, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed. Status Register The status register monitors the OTF and the state of the external enable pins dedicated to the TCXO and MOT LDOs. The MSM can periodically poll this register to determine their status. This is a read-only register.
(c) 2006 Semtech Corp. 12 www.semtech.com
Layout Considerations The PCB layout associated with the SC905A is straightforward, with the main consideration being given to the value and position of the input bypass capacitors. The device has eight input voltage pins which can be powered from a single supply or from a number of individual supplies depending on how much copper is available on the input voltage feed track and how much real estate is available on the PCB for components. If all the supply inputs are fed from one single supply trace or from a power plane, a 10F low ESR capacitor or two 4.7F low ESR capacitors should be used. Larger input capacitance and lower ESR provide better supply noise rejection and line transient response. The copper trace to the inputs should be fairly thick in order to keep trace inductance to a minimum and the capacitors should be located as close to the SC905A as possible. If the supply trace is thin then the inputs should be treated as if they were powered from individual supplies; each input should be bypassed by at least one 1F low ESR capacitor located very close to each input pin. The SC905A is designed to have excellent stability with a minimum output capacitance of 1F. Low ESR ceramic capacitors are recommended and should be located as close to the LDO output pins as possible.
SC905A
POWER MANAGEMENT Register Map
Register Name VPAD Register Address 0 1 Default State VCORE VMOT 1 2 X VMOT _EN 1 ON VANA /VCAM VTCXO/VRX VPLL /VTX ON/OFF CONTROL 3 4 5 6 0 OFF Bit 7 DSB
(1 )
Bit 6 X
Bit 5 X
Bit 4 VPAD 4
Bit 3 VPAD 3
Bit 2 VPAD 2
Bit 1 VPAD 1
Bit 0 VPAD 0
0 User State X VMOT Active SHDN 1 ON 0 OFF VANA0 VRX1 VTX1 VANA_EN 1 ON 0 OFF VCAM4 VRX0 VTX0 VCAM_EN 1 ON 0 OFF VCAM 3 X X VTCXO_EN 1 ON 0 OFF VCAM2 VTCXO2 VPLL2 VPLL_EN 1 ON 0 OFF VCAM1 VTCXO1 VPLL1 VTX_EN 1 ON 0 OFF VCAM 0 VTCXO0 VPLL0 VRX_EN 1 ON 0 OFF X X VCORE4 VMOT4 VCORE3 VMOT 3 VCORE2 VMOT2 VCORE1 VMOT1 VCORE0 VMOT 0
VANA2 X X VPAD _EN 1 ON 0 OFF
VANA1 VRX2 VTX2 VCORE_EN 1 ON 0 OFF
ACTIVE SHUTDOWN
(2 )
7
VPAD Active SHDN 1 ON 0 OFF X
VCORE Active SHDN 1 ON X 0 OFF
VANA Active SHDN 1 ON X 0 OFF
VCAM Active SHDN 1 ON X 0 OFF
VTCXO Active SHDN 1 ON OTF 1 OK 0 FAULT 0 OFF
VPLL Active SHDN 1 ON 0 OFF
VTX Active SHDN 1 ON 0 OFF
VRX Active SHDN 1 ON 0 OFF
STATUS (READ ONLY)
8
EN_MOT 1 ON 0 X OFF
EN_TCXO 1 ON 0 OFF
Defaults are indicated in BOLD.
SC905A Slave Address:
DEVICE ADDRESS 0 0 0 1 0 0 0 R/W X
Notes: (1) The default status bit (DSB) is set to 1 only when the SC905A is enabled by either the HFPWR pin or the ON pin being pulled high, and it cannot be set to one through the I2C interface. When changing the VPAD control voltage, always write to register 0 with bit seven high. Set bit seven low only when the DSB is to be cleared by the MSM. This will prevent any software race condition in a multi-tasking environment. See the applications section for more information on using the DSB. (2) The Active Shutdown defaults ON at power-up, but the registers maintain their settings as the LDOs are enabled and disabled during normal operation.
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SC905A
POWER MANAGEMENT Register Map (Cont.)
Digital LDO Voltage Tables A and B A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages for LDO CORE, and Table B for bitcodes and their corresponding voltages for LDOs PAD, MOT and CAM. TABLE A - Output Voltage Code Bits for VCORE
X4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LDO Output Voltage 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V 2.10V 2.15V 2.20V 2.25V 2.30V 2.35V 2.40V 2.45V 2.50V 2.55V 2.60V 2.65V 2.70V 2.75V 2.80V 2.85V 2.90V
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SC905A
POWER MANAGEMENT Register Map (Cont.)
TABLE B - Output Voltage Code Bits for VPAD, VMOT and VCAM
X4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LDO Output Voltage 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V 2.10V 2.15V 2.20V 2.25V 2.30V 2.35V 2.40V 2.45V 2.50V 2.55V 2.60V 2.65V 2.70V 2.75V 2.80V 2.85V 2.90V 2.95V 3.00V 3.05V 3.10V 3.15V 3.20V 3.25V 3.30V
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SC905A
POWER MANAGEMENT Register Map (Cont.)
Analog LDO Voltage Tables C and D The bit code controls the output voltage of each LDO. The LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table C for the bitcodes and their corresponding voltages for LDO ANA, and Table D for the bitcodes and their corresponding voltages for LDOs TCXO, TX, RX and PLL. TABLE C - Output Voltage Code Bits for LDO VANA
X2 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 LDO Output Voltage 2.55V 2.60V 2.65V 2.70V 2.75V 2.80V 2.85V 2.90V
TABLE D - Output Voltage Code Bits for LDOs VTCXO, VTX, VRX, VPLL
X2 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 LDO Output Voltage 2.75V 2.80V 2.85V 2.90V 2.95V 3.00V 3.05V 3.10V
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SC905A
POWER MANAGEMENT Using the I2C Serial Port
The I2C General Specification The SC905A is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated January, 2000. The SC905A has eight user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, in that once the slave address has been sent to the SC905A enabling it to be a slave transmitter/receiver, any register can be written or read independently of each other. While there is no auto increment/decrement capability in the SC905A I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. SC905A Limitations to the I2C Specifications Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by the SC905A. The SC905A is not CBUS compatible. The SC905A can operate in standard mode (100kbit/s) or fast mode (400kbit/s).
Supported Formats
Direct Format - Write The simplest format for an I2C write is given below. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905A I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P].
I2C Direct Format - Write
S
Slave Address
WA
Register Address
A
Data
AP
S: Start Condition W: Write = `0' A: Acknowledge (sent by slave) P: Stop condition
Slave Address: 7-bit Register Address: 8-bit Data: 8-bit
Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905A I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8-bit data byte; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P].
I2C Combined Format - Read
S
Slave Address
WA
Register Address
A Sr Slave Address R
A
Data
NACK P
S: Start Condition W: Write = `0' R: Read = `1' A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition
Slave Address: 7-bit Register Address: 8-bit Data: 8-bit
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SC905A
POWER MANAGEMENT Using the I2C Serial Port (Cont.)
Stop-Separated Reads Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The SC905A then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the SC905A with a read command. The SC905A acknowledges this request and returns the data from the register location that had previously been set up.
I2C Stop Separated Format- Read Register Address Setup Access Master Addresses other Slaves Register Read Access S/Sr Slave Address A R A Data NACK P
S Slave Address W A Register Address A P S Slave Address B S: Start Condition W: Write = `0' R: Read = `1' A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition Slave Address: 7-bit Register Address: 8-bit Data: 8-bit
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SC905A
POWER MANAGEMENT Timing Diagram
Power On-Off Timing Diagram
ON, HFPWR or CHPWR
MSM DETERMINED
DSB
BP
25ms 1.2V 25ms 77% 200s 77% 77% 100s 77%
VCORE
VPAD
100s 100s
VANA
100s
100ms 100s
100ms
VTCXO
RESB
MSM DETERMINED MSM DETERMINED
PGOOD
PWRON EN_TCXO
XXXXXXXX XXXXXXXX
XXXXXXXXXX XXXXXXXXXX
XXXX XXXX
EN_MOT
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SC905A
POWER MANAGEMENT Typical Characteristics
Dropout Voltage vs. Load Current (Analog LDOs)
200 175
Dropout Voltage vs. Load Current (Digital LDOs)
225 200
T = 85C
Dropout Voltage (mV)
T = 85C
Dropout Voltage (mV)
150 125 100 75
T = 25C
175 150 125 100 75
T = 25C
50 25 0 80 100 120 140 160 180 200
T = -40C
50 25 0 100
T = -40C
125
150
175
200
225
250
275
300
Load Current (mA)
Load Current (mA)
Load Regulation (Analog LDOs) VIN = 3.7V Output Voltage Variation (mV) Output Voltage Variation (mV)
0
T = 85C
Load Regulation (Digital LDOs) VIN = 3.7V
0
T = 85C
-3
-3
-6
-6
-9
T = -40C
-9
-12
T = -40C
-15
T = 25C
-12
T = 25C
-18 0 25 50 75 100 125 150 175 200
-15 0 50 100 150 200 250 300
Load Current (mA)
Load Current (mA)
Line Regulation (Analog LDOs) ILOAD = 1mA Output Voltage Variation (mV) Output Voltage Variation (mV)
5
Line Regulation (Digital LDOs) ILOAD = 1mA
6
4
T = 85C
5
T = 85C
4
T = 25C
3
T = 25C
3
2
2
1
T = -40C
1
T = -40C
0 3 3.5 4 4.5 5 5.5
0 3 3.5 4 4.5 5 5.5
Input Voltage (V)
Input Voltage (V)
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SC905A
POWER MANAGEMENT Typical Characteristics (Cont.)
PSRR vs. Frequency (Analog LDOs) VOUT = VOUT(MAX), VIN = 3.7V, ILOAD = 50mA
0
PSRR vs. Frequency (Digital LDOs) VOUT = VOUT(MAX), VIN = 3.7V, ILOAD = 50mA
0
Power Supply Rejection (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 10 100 1000 10000
Power Supply Rejection (dB)
-10 -20 -30 -40 -50 -60 -70 -80 10 100 1000 10000
Frequency (Hz)
Frequency (Hz)
Safe Operating Limits Maximum Outptu Current (A)
1.6 1.4
Output Noise vs. Load Current (Analog LDOs) VOUT = VOUT(MAX), VIN = 3.7V
45 40
T = 25C
Output Noise (V)
1.2 1 0.8 0.6 0.4 0.2 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9
35 30 25 20
T = 85C T = -40C
VOUT = 1.35V VOUT = 2.90V
15 10 5 0 0 25 50 75 100 125 150 175 200
Input Voltage (V)
Load Current (mA)
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SC905A
POWER MANAGEMENT Outline Drawing - MLPQ-32 5x5
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SC905A
POWER MANAGEMENT Land Pattern - MLPQ-32 5x5
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805)498-3804
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